Embodiments of the present disclosure relate to bonded semiconductor structures and fabrication methods thereof.
Planar semiconductor devices, such as memory cells, are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the semiconductor devices approach a lower limit, planar process and fabrication techniques become challenging and costly. A three-dimensional (3D) device architecture can address the density limitation in some planar semiconductor devices, for example, Flash memory devices.
A 3D semiconductor device can be formed by stacking semiconductor wafers or dies and interconnecting them vertically using, for instance, through-silicon vias (TSVs) or copper-to-copper (Cu—Cu) connections, so that the resulting structure acts as a single device to achieve performance improvements at reduced power and smaller footprint than conventional planar processes. Among the various techniques for stacking semiconductor substrates, hybrid bonding is recognized as one of the promising techniques because of its capability of forming high-density interconnects.